VLSI KoreaOpenTitan
Open silicon root-of-trust design with hardware, firmware, verification, and integration collateral.
lowRISC CICApache-2.0
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The Open Silicon Directory143 curated resources · 2,105 registry submissions · Source-linked metadata
Xschem
Xschem is a schematic editor for VLSI, ASIC, and analog custom designs with SPICE, VHDL, and Verilog netlisting backends.
Stefan Frederik SchippersGPL-2.0-or-later
ngspice
ngspice is an open-source SPICE simulator for electric and electronic circuits, including mixed-signal circuits.
ngspice projectHeterogeneous component licenses (COPYING)
openEMS
openEMS is a free, open-source FDTD electromagnetic field solver with Octave, MATLAB, and Python scripting interfaces.
openEMS ProjectGPL-3.0
GDSFactory
GDSFactory is a Python library that creates CAD files for photonics, analog, quantum, MEMS, PCB, and other hardware designs.
gdsfactory contributorsMIT
DEVSIM
DEVSIM is a finite-volume TCAD device simulator with Python scripting and user-specified partial differential equations.
DEVSIM LLCApache-2.0
3D-ICE
3D-ICE is a C thermal-emulator library for transient thermal analysis of vertically stacked integrated circuits with inter-tier microchannel liquid cooling.
EPFL Embedded Systems LaboratoryGPL-3.0
LiteX
A Python framework for composing buses, soft cores, peripherals, FPGA cores, and complete SoCs.
Enjoy-DigitalBSD-2-Clause
OpenTitan
Open silicon root-of-trust design with hardware, firmware, verification, and integration collateral.
lowRISC CICApache-2.0
Ibex
A configurable 32-bit RISC-V SystemVerilog core built for embedded control applications.
lowRISC CICApache-2.0
VexRiscv
A plugin-oriented 32-bit RISC-V CPU generator designed for configurable FPGA implementations.
SpinalHDL contributorsMIT
cocotb
A Python framework for writing coroutine-based testbenches for Verilog and VHDL designs.
cocotb projectBSD-3-Clause
RISCV-DV
A SystemVerilog and UVM random instruction generator for RISC-V processor verification.
CHIPS AllianceApache-2.0
Yosys
An open RTL synthesis framework extensible through scripts, frontends, backends, and C++ passes.
YosysHQISC
OpenROAD
An integrated RTL-to-GDS application spanning floorplanning, placement, CTS, and routing.
The OpenROAD ProjectBSD-3-Clause
IHP Open Source PDK
Open 130 nm SiGe BiCMOS PDK collateral for analog, mixed-signal, RF, and digital research.
IHP GmbHApache-2.0
Lambdapdk
A collection that presents multiple open PDKs through a common SiliconCompiler interface.
SiliconCompiler projectApache-2.0
LiteX
A Python framework for composing buses, soft cores, peripherals, FPGA cores, and complete SoCs.
Enjoy-DigitalBSD-2-Clause
Amaranth HDL
A Python HDL and toolchain connecting hardware description, simulation, and FPGA builds.
Amaranth projectBSD-2-Clause
Embench IoT
A suite of compact C workloads for comparing deeply embedded platforms without an operating system.
Embench Task Group · FOSSiGPL-3.0-only
CVA6
A configurable application-class 32/64-bit RISC-V core maintained by the OpenHW Group community.
OpenHW GroupSHL-0.51
Rocket Chip
A Chisel-based SoC generator with RISC-V cores, caches, interconnects, peripherals, and configuration infrastructure.
CHIPS AllianceApache-2.0
BOOM
An open out-of-order superscalar RISC-V core generator designed to compose with the Rocket Chip ecosystem.
Berkeley Architecture ResearchApache-2.0
NEORV32
A synthesizable VHDL RISC-V microcontroller SoC with processor, peripherals, bootloader, software framework, and documentation.
NEORV32 projectBSD-3-Clause
OpenPiton
A scalable manycore research platform with tiled architecture, cache coherence, synthesis, simulation, and FPGA collateral.
Princeton Parallel GroupBSD-3-Clause
NVDLA
An open deep-learning accelerator architecture with synthesizable hardware, software stack, specifications, and integration guidance.
NVIDIAApache-2.0
Gemmini
A generator for full-system matrix-multiplication accelerators integrated with the Chipyard and Rocket Chip ecosystem.
Berkeley Architecture ResearchApache-2.0
PULP AXI
Reusable SystemVerilog AXI4, AXI4-Lite, and stream components for open SoC integration and verification.
PULP PlatformSHL-0.51
RISC-V Formal
A formal verification framework and interface for checking RISC-V processor implementations against ISA properties.
YosysHQISC
Verilator
A fast SystemVerilog compiler, simulator, lint engine, and coverage tool for software-driven hardware verification.
Verilator projectLGPL-3.0-only OR Artistic-2.0
SymbiYosys
A front end for reproducible safety, liveness, cover, and equivalence flows using open formal engines.
YosysHQISC
Verible
A suite of SystemVerilog developer tools including parser, linter, formatter, language server, and syntax utilities.
CHIPS AllianceApache-2.0
FuseSoC
A package manager and build abstraction for reusable HDL cores across simulators, synthesis, FPGA, and ASIC tools.
CHIPS AllianceBSD-2-Clause
OpenLane 2
A configurable Python infrastructure for composing reproducible RTL-to-GDS flows around open and commercial EDA tools.
EfablessApache-2.0
KLayout
A layout viewer and editor with scripting, verification, format conversion, and integration APIs for IC design flows.
KLayout projectGPL-3.0-only
nextpnr
A portable, timing-driven FPGA place-and-route framework supporting multiple architectures and open device databases.
YosysHQISC
SKY130 Open PDK
An open-source 130 nm process design kit distribution for education, research, prototyping, and open tool development.
Google · SkyWaterApache-2.0
GF180MCU Open PDK
An open 180 nm mixed-signal MCU process design kit distribution with digital, analog, and high-voltage collateral.
Google · GlobalFoundriesApache-2.0
3D-ICE
3D-ICE is a C thermal-emulator library for transient thermal analysis of vertically stacked integrated circuits with inter-tier microchannel liquid cooling.
EPFL Embedded Systems LaboratoryGPL-3.0
AIGER
A format, library, and utilities for And-Inverter Graphs.
Armin BiereMIT
ALIGN
ALIGN automatically translates unannotated or partially annotated analog SPICE netlists to GDSII layout.
University of Minnesota, Texas A&M University, and Intel CorporationBSD-3-Clause
Analog (Integrated) Circuit Design
Analog (Integrated) Circuit Design is intermediate-level MOSFET circuit-design course material using Xschem, ngspice, and IHP SG13G2.
Johannes Kepler University Department for Integrated CircuitsApache-2.0
APB
An implementation of the AMBA APB4 protocol version 2.0.
PULP PlatformSolderpad-0.51
ASAP7 PDK and Cell Libraries
A repository providing ASAP7 PDK collateral and cell libraries.
The OpenROAD ProjectBSD-3-Clause
BAG
BAG is an analog and mixed-signal generator framework and successor to BAG_framework.
Blue Cheetah Analog DesignApache-2.0 (repository-wide); some files are Apache-2.0 AND BSD-3-Clause
BAG Framework
BAG Framework is Berkeley Analog Generator version 2.0 and later, a publicly released analog generator framework.
UC Berkeley ARTBSD-3-Clause
Bender
A dependency-management tool that resolves and locks HDL package source sets.
PULP PlatformMIT
Bitwuzla
An SMT solver for bit-vectors, floating-point arithmetic, arrays, and uninterpreted functions.
Bitwuzla contributorsMIT
Boolector
An SMT solver for fixed-size bit-vectors, arrays, and uninterpreted functions.
Boolector contributorsMIT
CACE
CACE is a framework for automatic analog and mixed-signal circuit characterization across conditions, Monte Carlo, and mismatch analysis.
efablessApache-2.0
Caliptra RTL
RTL and integration collateral documented by the upstream Caliptra hands-on guide.
CHIPS AllianceApache-2.0
ceviche
ceviche provides finite-difference frequency- and time-domain electromagnetic solvers compatible with automatic differentiation.
Ceviche Package ContributorsMIT
CharLib
CharLib is a characterization library for standard cells.
Stine JepsenGPL-2.0 (upstream COPYING or LICENSE)
Chipify
Chipify is a GUI and CLI wrapper for mismatch simulation, parameter sweeps, and yield analysis using Xschem and ngspice.
Santiago HofwimmerApache-2.0
Chisel
A Scala embedded HDL for parameterized RTL circuit generators that produce synthesizable Verilog for ASIC and FPGA logic.
CHIPS AllianceApache-2.0
Ciel
Ciel is a version manager and builder for open-source PDKs.
FOSSi FoundationApache-2.0
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Official sources. Open possibilities.External catalog · 2248 projects
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