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Browse github.com/amaranth-lang/amaranth
VLSI HUBAll resources FPGA / FPGA PROJECT SOURCE-LINKED RECORD
Amaranth project /
Amaranth HDL
A Python HDL and toolchain connecting hardware description, simulation, and FPGA builds.
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git clone https://github.com/amaranth-lang/amaranth.git01 / FILES & REVISIONSFiles from the source.
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Official license file
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Read BSD-2-Clause sourceUpstream activity
Main branch commit observed 2026-08-12
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02 / PROVENANCE & EVIDENCEInspect the evidence
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- 01
- 02LICENSE SOURCEBSD-2-Clause · official file ↗
- 03ACTIVITY SOURCEMain branch commit observed 2026-08-12 ↗
- 04CATALOG REVIEWReviewed 2026-08-18
03 / REPRODUCIBLE RUNS
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RUN STATUS / EMPTYNO HUB RUNS
VLSI Hub has not yet performed and recorded a build, simulation, synthesis, P&R, FPGA, or benchmark run for Amaranth HDL.
REQUIRED FOR A FUTURE RUN
- 01Pinned source revision
- 02Tool and environment versions
- 03Commands, constraints, and seed
- 04Logs and result artifacts
04 / COMMUNITYRoute discussion and contribution
Route discussion and contribution
to the upstream.
This release does not mirror or aggregate issues, pull requests, or participant counts.