Upstream file tree
Use the official repository as the authority for the current file and directory tree.
Browse github.com/chipsalliance/rocket-chipRTL / RISC-V CORE SOURCE-LINKED RECORD
CHIPS Alliance /
Rocket Chip
A Chisel-based SoC generator with RISC-V cores, caches, interconnects, peripherals, and configuration infrastructure.
CLONE UPSTREAM
git clone https://github.com/chipsalliance/rocket-chip.git01 / FILES & REVISIONSFiles from the source.
Files from the source.
History from the source.
This release does not mirror repository files or invent a local file listing. It links only to known official paths.
Official license file
This is the license-file path recorded by the catalog. Review the original text for its exact scope.
Read Apache-2.0 sourceUpstream activity
Official repository releases and activity
Inspect activity evidencePINNED REVISION
Not recorded in this catalog entry
This catalog entry does not name a specific tag or commit SHA. Pin a revision from the official repository before attempting reproduction.
02 / PROVENANCE & EVIDENCEInspect the evidence
Inspect the evidence
before the claim.
These fields are official upstream references and catalog observations—not an internal Hub certification.
- 01
- 02LICENSE SOURCEApache-2.0 · official file ↗
- 03ACTIVITY SOURCEOfficial repository releases and activity ↗
- 04CATALOG REVIEWReviewed 2026-08-22
03 / REPRODUCIBLE RUNS
No Hub run is attached yet.
We do not invent measurements or relabel upstream results as Hub executions.
RUN STATUS / EMPTYNO HUB RUNS
VLSI Hub has not yet performed and recorded a build, simulation, synthesis, P&R, FPGA, or benchmark run for Rocket Chip.
REQUIRED FOR A FUTURE RUN
- 01Pinned source revision
- 02Tool and environment versions
- 03Commands, constraints, and seed
- 04Logs and result artifacts
04 / COMMUNITYRoute discussion and contribution
Route discussion and contribution
to the upstream.
This release does not mirror or aggregate issues, pull requests, or participant counts.