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Browse github.com/stnolting/neorv32FPGA / RISC-V CORE SOURCE-LINKED RECORD
NEORV32 project /
NEORV32
A synthesizable VHDL RISC-V microcontroller SoC with processor, peripherals, bootloader, software framework, and documentation.
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git clone https://github.com/stnolting/neorv32.git01 / FILES & REVISIONSFiles from the source.
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Official license file
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Read BSD-3-Clause sourceUpstream activity
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02 / PROVENANCE & EVIDENCEInspect the evidence
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before the claim.
These fields are official upstream references and catalog observations—not an internal Hub certification.
- 01UPSTREAMgithub.com/stnolting/neorv32 ↗
- 02LICENSE SOURCEBSD-3-Clause · official file ↗
- 03ACTIVITY SOURCEOfficial repository releases and activity ↗
- 04CATALOG REVIEWReviewed 2026-08-22
03 / REPRODUCIBLE RUNS
No Hub run is attached yet.
We do not invent measurements or relabel upstream results as Hub executions.
RUN STATUS / EMPTYNO HUB RUNS
VLSI Hub has not yet performed and recorded a build, simulation, synthesis, P&R, FPGA, or benchmark run for NEORV32.
REQUIRED FOR A FUTURE RUN
- 01Pinned source revision
- 02Tool and environment versions
- 03Commands, constraints, and seed
- 04Logs and result artifacts
04 / COMMUNITYRoute discussion and contribution
Route discussion and contribution
to the upstream.
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