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Browse github.com/PrincetonUniversity/openpitonSYSTEM / OPEN CHIP DESIGN SOURCE-LINKED RECORD
Princeton Parallel Group /
OpenPiton
A scalable manycore research platform with tiled architecture, cache coherence, synthesis, simulation, and FPGA collateral.
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02 / PROVENANCE & EVIDENCEInspect the evidence
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- 02LICENSE SOURCEBSD-3-Clause · official file ↗
- 03ACTIVITY SOURCEOfficial repository releases and activity ↗
- 04CATALOG REVIEWReviewed 2026-08-22
03 / REPRODUCIBLE RUNS
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RUN STATUS / EMPTYNO HUB RUNS
VLSI Hub has not yet performed and recorded a build, simulation, synthesis, P&R, FPGA, or benchmark run for OpenPiton.
REQUIRED FOR A FUTURE RUN
- 01Pinned source revision
- 02Tool and environment versions
- 03Commands, constraints, and seed
- 04Logs and result artifacts
04 / COMMUNITYRoute discussion and contribution
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