SYSTEM / OPEN CHIP DESIGN01
lowRISC CIC /
OpenTitan
Open silicon root-of-trust design with hardware, firmware, verification, and integration collateral.
- TARGET
- Silicon root of trust
- TOOLCHAIN
- Bazel · Verilator
OPEN SILICON COMMONS Designs · Data · Labs
칩을 만드는 모든
오픈소스, 한곳에서.
Hugging Face가 AI의 모델·데이터·앱을 연결하듯, 설계·검증·PDK·EDA·실행 결과와 논문 재현을
하나의 증거 그래프로 연결하는 오픈 실리콘 허브입니다.
Try
HUGGING FACE → OPEN SILICON
THE COMPLETE HUB MAP
Every major Hub primitive, translated for semiconductor artifacts, execution and evidence.
Live on this Hub Official upstream bridge Isolated runner required
01LIVE
MODEL REPOSITORIESDESIGN REPOSITORIESRTL, IP, cores, SoCs and FPGA designs with stable artifact pages.
↘02LIVE
DATASETS + DATA STUDIOPDKS, BENCHMARKS + RESULT STUDIOProcess collateral, workloads, traces and comparable run records.
↘03UPSTREAM BRIDGE
SPACESSILICON LABSPinned simulation, formal, FPGA and RTL-to-GDS recipe blueprints.
↘04LIVE
MODEL + DATASET CARDSARTIFACT PASSPORTSInterfaces, targets, licenses, limitations and evidence in one card.
↘05LIVE
EVALUATIONS + LEADERBOARDSVERIFICATION + PPA RECORDSOnly like-for-like results, tied to design, tool, target and corner.
↘06LIVE
COLLECTIONSVERSIONED DESIGN STACKSCore, VIP, PDK, flow and benchmark paths grouped with context.
↘07LIVE
PAPER PAGESPAPERS + REPRODUCTIONSPaper, source, environment, evidence and deviation report linked.
↘08LIVE
LIKES + FOLLOWINGMY BENCHDevice-local saves and a three-way artifact comparison bench.
↘09UPSTREAM BRIDGE
DISCUSSIONS + PULL REQUESTSDESIGN REVIEWSQuestions, issues and contributions continue in official upstreams.
↘10LIVE
ORGANIZATIONS + PROFILESLABS, FOUNDATIONS + MAINTAINERSSource-linked organization directory without invented popularity.
↘11UPSTREAM BRIDGE
SECURITY + GATED REPOSTRUST + LICENSE GATESExplicit redistribution scope, provenance and evidence boundaries.
↘12RUNNER REQUIRED
JOBS + ENDPOINTS + BUCKETSEDA RUNS, APIS + RUN STORAGEIsolated compute, immutable logs and large artifacts need real runners.
↘13RUNNER REQUIRED
AGENTS + MCP + SKILLSVLSI MCP + DESIGN SKILLSSearch, dependency resolution, runs and evidence submission by tools.
↘THE SILICON STACK
설계의 전 과정을 탐색하세요.
UNIFIED ARTIFACT REGISTRY
저장소가 아니라, 설계 계보를 찾으세요.
공식 업스트림, 라이선스, 설계 맥락과 실행 증거를 같은 검색 표면에서 탐색합니다.
External index · not hosted by VLSI Hub
RTL / RISC-V CORE02
lowRISC CIC /
Ibex
A configurable 32-bit RISC-V SystemVerilog core built for embedded control applications.
- TARGET
- RV32 embedded
- TOOLCHAIN
- FuseSoC · Verilator
RTL / RISC-V CORE03
SpinalHDL contributors /
VexRiscv
A plugin-oriented 32-bit RISC-V CPU generator designed for configurable FPGA implementations.
- TARGET
- FPGA · RV32
- TOOLCHAIN
- SpinalHDL · Verilator
VERIFY / VERIFICATION04
cocotb project /
cocotb
A Python framework for writing coroutine-based testbenches for Verilog and VHDL designs.
- TARGET
- Verilog · VHDL
- TOOLCHAIN
- Multiple simulators
VERIFY / VERIFICATION05
CHIPS Alliance /
RISCV-DV
A SystemVerilog and UVM random instruction generator for RISC-V processor verification.
- TARGET
- RISC-V ISA
- TOOLCHAIN
- UVM · ISS co-sim
SYNTH / OPEN EDA06
YosysHQ /
Yosys
An open RTL synthesis framework extensible through scripts, frontends, backends, and C++ passes.
- TARGET
- RTL synthesis
- TOOLCHAIN
- Verilog · RTLIL · Tcl
PHYSICAL / OPEN EDA07
The OpenROAD Project /
OpenROAD
An integrated RTL-to-GDS application spanning floorplanning, placement, CTS, and routing.
- TARGET
- Physical design
- TOOLCHAIN
- LEF · DEF · GDS
PDK / OPEN PDK08
IHP GmbH /
IHP Open Source PDK
Open 130 nm SiGe BiCMOS PDK collateral for analog, mixed-signal, RF, and digital research.
- TARGET
- SG13G2 · 130 nm
- TOOLCHAIN
- KLayout · ngspice · OpenROAD
PDK / OPEN PDK09
SiliconCompiler project /
Lambdapdk
A collection that presents multiple open PDKs through a common SiliconCompiler interface.
- TARGET
- Multiple process nodes
- TOOLCHAIN
- SiliconCompiler
FPGA / FPGA PROJECT10
Enjoy-Digital /
LiteX
A Python framework for composing buses, soft cores, peripherals, FPGA cores, and complete SoCs.
- TARGET
- Multi-vendor FPGA
- TOOLCHAIN
- Vendor + open flows
FPGA / FPGA PROJECT11
Amaranth project /
Amaranth HDL
A Python HDL and toolchain connecting hardware description, simulation, and FPGA builds.
- TARGET
- FPGA · simulation
- TOOLCHAIN
- Yosys · nextpnr · vendor tools
REPRO / BENCHMARK12
Embench Task Group · FOSSi /
Embench IoT
A suite of compact C workloads for comparing deeply embedded platforms without an operating system.
- TARGET
- Embedded platforms
- TOOLCHAIN
- SCons · C toolchain
MY BENCH / DEVICE LOCAL
COMPARE ARTIFACT CONTEXT
Select up to three artifacts. Conditions and provenance stay visible; popularity is never treated as quality.
0 / 3Use Compare on any repository card to build a context table.
SPACES → SILICON LABS
실행은 레시피부터 고정합니다.
현재는 공식 업스트림으로 연결되는 재현 레시피 청사진입니다. 실제 EDA 실행이나 성공을 주장하지 않습니다.
Isolated runner required for real execution
01 / SPACE → LABRECIPE BLUEPRINT
RTL SIMULATION LAB
cocotb + VerilatorPin a DUT, simulator image, tests and seeds; retain logs, JUnit and waveforms.
RUN MANIFESTTEST LOGWAVEFORMCOVERAGE
02 / SPACE + JOB → LAB + RUNRECIPE BLUEPRINT
RTL-TO-GDS LAB
Yosys + OpenROAD + Open PDKBind design, flow and target fingerprints before any timing or area comparison.
LOCKFILEREPORTSDEF / GDSRESULT JSON
03 / SPACE + ENDPOINT → LAB + APIRECIPE BLUEPRINT
FPGA BUILD LAB
LiteX + board toolchainGenerate a board-specific recipe with part, package, speed grade and constraints.
RECIPETIMINGUTILIZATIONBITSTREAM POINTER
REPRODUCIBLE BY DESIGN
조건까지 투명한 벤치마크.
서로 다른 공정·툴·코너의 숫자를 섞지 않고, 실행 조건과 원본 산출물을 결과보다 먼저 보여줍니다.
BENCHMARK RUNS / PREVIEWIllustrative schema — no measured values published
DEMO STRUCTURE| PROJECT | TARGET | TOOLCHAIN | METRIC | RESULT | CONDITION | STATUS |
|---|---|---|---|---|---|---|
| demo/rv32-core | Generic 130 nm | Yosys + OpenROAD | Fmax | — | TT · 25°C | Awaiting run |
| demo/axi-crossbar | Artix-7 class | Open FPGA flow | LUT | — | Default seed | Awaiting run |
| demo/uart-vip | RTL simulation | cocotb + Verilator | Tests | — | Pinned image | Awaiting run |
01PIN EVERY VERSION
Design, tool, image, and seed.
02DECLARE CONTEXT
Node, library, corner, and constraints.
03PUBLISH ARTIFACTS
Logs, reports, and machine-readable results.
04COMPARE LIKE WITH LIKE
Different conditions stay visibly separate.
CURATED PATHS
프로젝트를 넘어, 도구 체인으로.
한 개의 저장소가 아니라 실제 설계 흐름에 필요한 리소스를 맥락과 함께 묶습니다.
Open RISC-V Core Stack
코어 선택부터 랜덤 명령 검증과 Python 테스트벤치까지 이어지는 공개 프로젝트 묶음.
Open Digital Flow
합성, 물리 설계, 공개 PDK 인터페이스로 연결되는 오픈 ASIC 도구 체인.
FPGA Design Path
Python HDL과 SoC 프레임워크, 코어와 임베디드 벤치마크를 한 흐름으로 탐색합니다.
PAPER PAGES → REPRODUCTIONS
논문과 설계, 결과를 한 페이지에.
원문과 공개 소스를 연결하되, 허브가 직접 재현하지 않은 결과는 재현으로 표시하지 않습니다.
IEEE TVLSI · 2019
SOURCE LINKED · NO HUB REPRODUCTIONThe Cost of Application-Class Processing
CVA6 / Ariane · energy and performance
ICCAD · 2020
SOURCE LINKED · NO HUB REPRODUCTIONBuilding OpenLANE
130 nm OpenROAD-based RTL-to-GDS flow
GOMACTech · 2019
SOURCE LINKED · NO HUB REPRODUCTIONOpenROAD: Toward a Self-Driving Tool Chain
Open-source autonomous digital implementation
ORGANIZATIONS + MAINTAINERS
업스트림을 만든 사람과 조직부터.
팔로워 수 대신 공식 출처, 역할과 유지관리 범위를 보여주는 조직 디렉터리입니다.
01 / OPEN SILICON
lowRISC CIC
OpenTitan · Ibex
Official organization ↗02 / FOUNDATIONCHIPS Alliance
RTL · DV · EDA
Official organization ↗03 / FOUNDATIONOpenHW Group
CORE-V · CVA6
Official organization ↗04 / OPEN EDAYosysHQ
Synthesis · formal · FPGA
Official organization ↗05 / OPEN EDAThe OpenROAD Project
RTL-to-GDS
Official organization ↗06 / COMMUNITYFOSSi Foundation
Open source silicon
Official organization ↗07 / RESEARCH FABIHP GmbH
SG13G2 open PDK
Official organization ↗DISCUSSIONS + PULL REQUESTS → DESIGN REVIEWS
대화도 증거가 있는 곳에서.
이 인덱스는 토론 수를 꾸며내지 않습니다. 각 패스포트의 Community 탭에서 공식 업스트림 이슈와 Pull Request로 바로 연결합니다.
01QUESTION
Ask against an exact artifact and release.
02CHANGE
Review source and constraints in the upstream PR.
03REPRODUCTION
Attach recipe, logs, outputs and deviations.
04EVIDENCE
State who ran what, where, when and with which hash.
SECURITY + GATING → TRUST CONTRACT
단일 Verified 배지 대신, 확인한 범위를 공개합니다.
소스, 매니페스트, 빌드, 테스트, formal, PPA와 실리콘 증거는 서로 다른 주장입니다.
| BADGE | EXACT MEANING | THIS RELEASE |
|---|---|---|
| SOURCE LINKED | Official upstream and review date are identified. | AVAILABLE |
| MANIFEST VALIDATED | Required metadata and referenced files resolve. | NOT CLAIMED |
| HUB BUILD REPRODUCED | A pinned recipe completed on an identified runner. | NOT CLAIMED |
| HUB TESTS REPRODUCED | Declared tests passed with logs and checksums. | NOT CLAIMED |
| PPA RESULT REPRODUCED | Reports regenerated under one target fingerprint. | NOT CLAIMED |
| SILICON EVIDENCE CORROBORATED | An identified independent party checked evidence. | NOT CLAIMED |
RUNNER-BACKED PLATFORM LAYER
REAL INFRASTRUCTURE, NOT A FAKE BUTTON
These surfaces are fully specified here, but remain unavailable until isolated compute, storage, identity and policy controls exist.
RESULT STUDIO
Logs, waveforms, netlists, floorplans, tables and machine-readable evidence.
REVIEW + NOTIFY
Discussion, PR, watch, follow, mention and release activity with moderation.
EDA JOBS + ENDPOINTS
Network-off isolated lint, simulation, formal, synthesis, P&R and FPGA jobs.
RUN STORAGE
Large mutable waveforms, logs, databases and cache outside version history.
VLSI MCP + SKILLS
Search, dependency resolution, run control, comparison and evidence submission.
ORG SECURITY
Gated artifacts, SSO, resource groups, audit logs and export-control review.
WHY VLSI HUB저장소 목록보다
저장소 목록보다
한 단계 더 깊게.
Provenance first
어디에서 온 파일인지, 어떤 버전과 라이선스인지 먼저 확인합니다.
Context before ranking
PPA와 테스트 결과는 공정, 라이브러리, 툴, 코너가 같을 때만 직접 비교합니다.
Runs as first-class records
커밋, 환경, 명령, 로그, 산출물을 연결해 다른 사람이 다시 실행할 수 있게 합니다.
CONTRIBUTE TO THE COMMONS
당신의 설계를 다음 프로젝트의 출발점으로.
공식 소스, 고정 버전, 라이선스, 실행 방법과 검증 범위를 vlsi.yaml 하나로 준비하세요. 파일 업로드 없이 External index부터 시작합니다.
매니페스트 체크리스트 보기
- 01Public source repository
- 02Pinned release or commit
- 03SPDX expression and redistribution scope
- 04Build, simulation or reproduction recipe
- 05Evidence boundary and known limitations