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Browse github.com/verilator/verilatorVERIFY / OPEN EDA SOURCE-LINKED RECORD
Verilator project /
Verilator
A fast SystemVerilog compiler, simulator, lint engine, and coverage tool for software-driven hardware verification.
CLONE UPSTREAM
git clone https://github.com/verilator/verilator.git01 / FILES & REVISIONSFiles from the source.
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Official license file
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Read LGPL-3.0-only OR Artistic-2.0 sourceUpstream activity
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02 / PROVENANCE & EVIDENCEInspect the evidence
Inspect the evidence
before the claim.
These fields are official upstream references and catalog observations—not an internal Hub certification.
- 01UPSTREAMgithub.com/verilator/verilator ↗
- 02LICENSE SOURCELGPL-3.0-only OR Artistic-2.0 · official file ↗
- 03ACTIVITY SOURCEOfficial repository releases and activity ↗
- 04CATALOG REVIEWReviewed 2026-08-22
03 / REPRODUCIBLE RUNS
No Hub run is attached yet.
We do not invent measurements or relabel upstream results as Hub executions.
RUN STATUS / EMPTYNO HUB RUNS
VLSI Hub has not yet performed and recorded a build, simulation, synthesis, P&R, FPGA, or benchmark run for Verilator.
REQUIRED FOR A FUTURE RUN
- 01Pinned source revision
- 02Tool and environment versions
- 03Commands, constraints, and seed
- 04Logs and result artifacts
04 / COMMUNITYRoute discussion and contribution
Route discussion and contribution
to the upstream.
This release does not mirror or aggregate issues, pull requests, or participant counts.