VLSI KoreaSEMICONDUCTOR ENGINEERING
From architecture to physical implementation
Source-linked inputs, methods and deliverables for each design stage.Performance Architecture: Roofline and Memory Budget
Turn workload counts and data movement into a bounded performance target before choosing pipelines or memory structures. This is generic guidance, not a description of any commercial chip’s undisclosed implementation.
rtlRTL Microarchitecture: Pipelines, Backpressure, and Protocol Contracts
Make each stage’s acceptance, storage, ordering, and flush behavior explicit. The ready/valid rules below apply to a chosen compatible protocol; interface-specific requirements remain authoritative.
verificationVerification Plan: Executable Contracts, Coverage, and Formal
Connect requirements to simulation checks, coverage, and bounded or unbounded proofs. A passing proof is meaningful only under reviewed environment assumptions and reachable scenarios.
clock-resetCDC/RDC and Clock/Reset Architecture
Treat clocks, resets, and power transitions as named architectural interfaces with ownership and acknowledgement. The patterns are generic; synchronization depth and constraints require technology, MTBF, and flow-specific analysis.
low-powerLow-Power Architecture: UPF Intent and Power-State Verification
Specify power intent alongside RTL so domains, supplies, isolation, retention, and allowed states can be verified consistently. UPF captures intent; actual command syntax and signoff criteria depend on the adopted IEEE revision and tool flow.
synthesisTurn RTL Intent into a Checkable Netlist
Build one traceable contract from RTL through SDC, synthesis, and equivalence. Open-source results teach the loop; a production release still needs the project’s qualified libraries, modes, corners, and approved formal setup.
dftPlan Scan as a Physical and Security-Aware Feature
Treat scan architecture, test access, timing, and physical stitching as one design decision. Use the open flow to learn ordering; coverage targets, ATPG, test protocol, memory BIST, and production signoff remain program-specific.
floorplanMake the Floorplan Feasible Before Optimizing It
Start with geometry, interfaces, macro access, and power-return paths. Open-source PDN analysis gives early evidence; final bump/package models, reliability limits, and foundry rules must come from the qualified project flow.
implementationClose Timing with Physical Evidence
Use each implementation stage to replace estimates with evidence: congestion after placement, skew after CTS, and wire RC after routing. Fix root causes through a controlled loop and preserve proof that every change helped the intended corner.
signoffAssemble a Reproducible Signoff Evidence Package
A tapeout decision is a set of versioned evidence, not a green dashboard. Educational open-source DRC/LVS/RC/IR runs are valuable cross-checks, while qualified foundry decks, extraction, reliability rules, and customer signoff criteria remain authoritative.