SIGNOFF
Assemble a Reproducible Signoff Evidence Package
A tapeout decision is a set of versioned evidence, not a green dashboard. Educational open-source DRC/LVS/RC/IR runs are valuable cross-checks, while qualified foundry decks, extraction, reliability rules, and customer signoff criteria remain authoritative.Inputs
- Final layout/netlist, fill state, and exact release manifest
- Qualified multi-corner libraries, RC tech files, and SDC
- Foundry-approved DRC/LVS/antenna/reliability decks and waiver policy
Method
- Freeze hashes for layout, netlist, constraints, libraries, extraction inputs, decks, tool versions, and run settings before final analysis.
- Extract parasitics at each required corner and run propagated-clock STA for setup, hold, recovery/removal, pulse width, and unconstrained-path review.
- Run the qualified physical-verification decks and triage every DRC, LVS, antenna, density, and connectivity result to disposition.
- Run IR/EM with approved activity, package, voltage-source, temperature, and lifetime assumptions; correlate hotspots to layout ownership.
- Review only bounded, justified waivers; issue a release matrix listing each check, scenario, result, owner, and reproducible command manifest.
Deliverables
- Corner/mode STA summary with full violation disposition
- Qualified DRC/LVS/antenna/extraction and IR/EM reports
- Immutable release manifest and signoff matrix
Pitfalls
- Using an STA netlist or SPEF that no longer corresponds to the post-fill layout verified by LVS breaks signoff correlation. Keep the RC corner and extraction setup consistent with each corresponding STA scenario.
- Open-source checks can reveal integration defects but cannot certify compliance with a proprietary foundry deck or undisclosed chip requirements.
Sources
OpenLane Architecture ↗
OpenLane · Open-source RTL-to-GDS stages and checks
SkyWater SKY130 Parasitic Layout Extraction ↗
SkyWater PDK · Parasitic resistance and capacitance extraction rules
IR Drop Analysis ↗
OpenROAD · Static IR/EM and floating-grid checks
Debugging timing ↗
OpenSTA · Constrained and unconstrained timing reports