RTL

RTL Microarchitecture: Pipelines, Backpressure, and Protocol Contracts

Make each stage’s acceptance, storage, ordering, and flush behavior explicit. The ready/valid rules below apply to a chosen compatible protocol; interface-specific requirements remain authoritative.

Inputs

Transaction ordering, throughput, and latency contract
Burst, error, reset, and cancellation semantics
Per-stage storage and downstream stall assumptions

Method

Write a one-page contract: what constitutes acceptance, whether responses may reorder, and which state is committed on a transfer.
Give every pipeline boundary an explicit register or elastic buffer and prove its capacity under worst expected stalls.
Keep payload stable while valid is asserted and advance state only on a completed transfer; propagate backpressure deliberately.
Define reset/flush priority and specify what happens to accepted-but-unanswered work; test it at every stage boundary.
Separate protocol adapters from computation so interface changes do not silently alter datapath correctness.

Deliverables

Cycle-level stage and buffering diagram
Interface contract and reset/flush table
Directed stall, burst, and recovery tests

Pitfalls

Creating a combinational ready/valid loop across modules.
Dropping or changing payload during backpressure.

Sources

AMBA AXI Protocol Specification ↗
Arm · A2.3 Valid-Ready transport