FLOORPLAN

Make the Floorplan Feasible Before Optimizing It

Start with geometry, interfaces, macro access, and power-return paths. Open-source PDN analysis gives early evidence; final bump/package models, reliability limits, and foundry rules must come from the qualified project flow.

Inputs

Die/core targets, I/O plan, and utilization budget
Macro LEF/abstracts, pin locations, blockages, and power intent
Technology routing stack and qualified power/current assumptions

Method

Set die/core geometry and row/tracks in technology units, then reserve edge and channel space for I/O, macros, and routing access.
Place macros from traffic and pin access, not only area; orient them to shorten dominant buses and keep feedthrough corridors.
Draft rings, straps, rails, and taps with explicit supply nets; review continuity and macro power-pin reachability.
Run early static IR and current-density checks with declared voltage sources and activity assumptions; feed hotspots back into PDN or placement.
Lock macro coordinates only after congestion, power, and timing feasibility reviews agree on the trade-off.

Deliverables

Versioned floorplan DEF with macro, blockage, and I/O intent
PDN specification and connectivity/floating-grid report
Early IR/EM assumption sheet and hotspot map

Pitfalls

High average utilization can still fail at macro corners and pin-dense channels.
Static open-flow IR analysis does not replace package-aware dynamic IR/EM signoff under qualified foundry reliability rules.

Sources

Initialize Floorplan ↗
OpenROAD · Floorplan geometry and tracks

IR Drop Analysis ↗
OpenROAD · Static IR/EM and floating-grid checks

OpenLane Architecture ↗
OpenLane · Open-source RTL-to-GDS stages and checks