DFT

Plan Scan as a Physical and Security-Aware Feature

Treat scan architecture, test access, timing, and physical stitching as one design decision. Use the open flow to learn ordering; coverage targets, ATPG, test protocol, memory BIST, and production signoff remain program-specific.

Inputs

Clock/reset domains and test-mode requirements
Scan-capable library cells and test I/O budget
Security and lifecycle rules for test access

Method

Partition scan chains by clock edge and power/test policy; decide consciously whether clock mixing is permitted.
Reserve scan-enable, scan-in, scan-out, test-clock, and reset behavior in the top-level contract before port freeze.
Replace flops, then use a placement-aware chain plan; inspect chain length balance and long physical hops before stitching.
Validate shift/capture constraints and test-mode isolation in simulation/formal checks, including safe behavior around secrets and NVM.
Publish a chain manifest and hand it to ATPG/test owners with explicit tool/version and waiver provenance.

Deliverables

Scan architecture and top-level test-port specification
Placed scan-chain manifest and connectivity report
Test-mode timing/isolation review and ATPG handoff package

Pitfalls

Stitching before placement can create avoidable wirelength and congestion.
Scan access can expose state or disturb live logic; lifecycle-controlled test enable is an architectural requirement, not merely a test convenience.

Sources

DFT: Design for Testing ↗
OpenROAD · Scan configuration, replacement, planning and stitching

Life Cycle Controller: Theory of Operation ↗
OpenTitan · DFT enable and test isolation