LOW-POWER

Low-Power Architecture: UPF Intent and Power-State Verification

Specify power intent alongside RTL so domains, supplies, isolation, retention, and allowed states can be verified consistently. UPF captures intent; actual command syntax and signoff criteria depend on the adopted IEEE revision and tool flow.

Inputs

Power goals, use cases, and transition latency/data-loss tolerance
Power-domain ownership, supply relationships, and interface directions
Retention candidates and software/firmware control protocol

Method

Start with a power-state table that lists legal states, supply status, clock status, isolation values, retention behavior, and entry/exit owner.
Partition domains by independently controllable power behavior and interface consequences, not merely hierarchy names.
For every powered-down output, define isolation direction, clamp value, enable timing, and acknowledgement before the consumer observes it.
Classify state as reset, retained, recomputed, or software-restored; verify save/restore ordering and invalid-data containment.
Use power-aware tests for every state transition and assertion checks for isolation/retention contracts; review intent after hierarchy integration.

Deliverables

Power-state and transition table
Reviewed UPF intent with domain/interface map
Power-aware transition tests and results

Pitfalls

Adding isolation after interfaces are finalized, with no defined clamp semantics.
Retaining data without defining which control state is restored and when it becomes valid.

Sources

Tutorial: Low Power Design, Verification, and Implementation with IEEE 1801 UPF ↗
Accellera · Tutorial description, Parts 2–6