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2:1 MUX

Icarus Verilog version 13.0 (stable) (v13_0) · CC0-1.0 (authored example source)

Design

// VLSI Hub authored example, CC0-1.0.
module mux2(input logic a, b, sel, output logic y);
  assign y = sel ? b : a;
endmodule

Download design.sv

Testbench

// VLSI Hub authored example, CC0-1.0.
`timescale 1ns/1ps
module tb;
  logic a, b, sel, y;
  mux2 dut(.*);
  initial begin
    $dumpfile("wave.vcd"); $dumpvars(0, tb);
    for (int i = 0; i < 8; i++) begin
      {sel, b, a} = i[2:0]; #5;
      if (y !== (sel ? b : a)) $fatal(1, "MUX assertion failed at vector %0d", i);
    end
    if ($test$plusargs("negative_control")) $fatal(1, "Expected negative-control failure");
    $display("PASS: MUX checked all 8 input vectors"); $finish;
  end
endmodule

Download tb.sv

Recorded console

VCD info: dumpfile wave.vcd opened for output.
PASS: MUX checked all 8 input vectors
tb.sv:13: $finish called at 40000 (1ps)

Simulation exit: 0. The intentional assertion failure returned exit 1; invalid compilation returned exit 1.

Full run log Negative-control evidence

Recorded waveform

Retained VCD data. Scalar traces show logic levels; bus values are decimal. Download the VCD to inspect every signal and four-state value.

Download VCD waveform →

Reproduce this exact source

sha256:b605b48b119ddc28681ef6aa0873e68652db99b5b18501b615a1ae9e7cb3c4cc

Download both source files into the same directory, then use the recorded command with the displayed tool version.

iverilog -g2012 -s tb -o sim design.sv tb.sv && vvp sim

Local darwin arm64 · trusted authored examples · no network dependencies

Each process: 5-second deadline, 1 MB console cap. No PDK or physical implementation.

Recorded: 2026-10-13T16:32:59.945Z. Example execution does not validate any catalog resource, PDK or silicon implementation.