// VLSI Hub authored example, CC0-1.0.
`timescale 1ns/1ps
module tb;
  logic a, b, sel, y;
  mux2 dut(.*);
  initial begin
    $dumpfile("wave.vcd"); $dumpvars(0, tb);
    for (int i = 0; i < 8; i++) begin
      {sel, b, a} = i[2:0]; #5;
      if (y !== (sel ? b : a)) $fatal(1, "MUX assertion failed at vector %0d", i);
    end
    if ($test$plusargs("negative_control")) $fatal(1, "Expected negative-control failure");
    $display("PASS: MUX checked all 8 input vectors"); $finish;
  end
endmodule