RTL Playground

Design

// VLSI Hub authored example, CC0-1.0.
module counter4(input logic clk, rst, output logic [3:0] count);
  always_ff @(posedge clk) begin
    if (rst) count <= 4'b0;
    else count <= count + 1'b1;
  end
endmodule

Testbench

// VLSI Hub authored example, CC0-1.0.
`timescale 1ns/1ps
module tb;
  logic clk = 0, rst = 1;
  logic [3:0] count;
  counter4 dut(.*);
  always #5 clk = ~clk;
  initial begin
    $dumpfile("wave.vcd"); $dumpvars(0, tb);
    @(posedge clk); #1;
    if (count !== 0) $fatal(1, "Reset assertion failed");
    @(negedge clk); rst = 0;
    for (int i = 1; i <= 18; i++) begin
      @(posedge clk); #1;
      if (count !== (i % 16)) $fatal(1, "Counter assertion failed at step %0d", i);
    end
    @(negedge clk); rst = 1;
    @(posedge clk); #1;
    if (count !== 0) $fatal(1, "Second reset assertion failed");
    if ($test$plusargs("negative_control")) $fatal(1, "Expected negative-control failure");
    $display("PASS: counter checked reset, 18 cycles, wraparound and second reset"); $finish;
  end
endmodule

Recorded console

VCD info: dumpfile wave.vcd opened for output.
PASS: counter checked reset, 18 cycles, wraparound and second reset
tb.sv:21: $finish called at 196000 (1ps)

Simulation exit: 0. The intentional assertion failure returned exit 1; invalid compilation returned exit 1.