VLSI KoreaEVIDENCE BEFORE MEASUREMENTS
Reproducibility & Benchmarks
Each result retains its source, tool, environment, command, exit status, log and waveform. A local example test is distinct from a catalog project reproduction.
| Example | Tool / scope | Result | Artifacts |
|---|---|---|---|
| 2:1 MUX
| Icarus Verilog version 13.0 (stable) (v13_0) Local darwin arm64 · trusted authored examples · no network dependencies 2026-10-13T16:32:59.945Z | Assertions passed · exit 0 Intentional failure: exit 1 | Run log VCD Negative controls |
| 4-bit counter
| Icarus Verilog version 13.0 (stable) (v13_0) Local darwin arm64 · trusted authored examples · no network dependencies 2026-10-13T16:32:59.980Z | Assertions passed · exit 0 Intentional failure: exit 1 | Run log VCD Negative controls |
No comparable measured PPA result
No area, frequency, power or routing benchmark is attached. These examples are functional simulations. Future PPA comparisons require matching source/configuration, tool versions, libraries, PDK revision, corners, voltage, temperature, constraints and units.