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9 results for “RISC-V”
Open silicon
RISC-V Formal
A formal verification framework and interface for checking RISC-V processor implementations against ISA properties.
Open silicon
BOOM
An open out-of-order superscalar RISC-V core generator designed to compose with the Rocket Chip ecosystem.
Open silicon
CVA6
A configurable application-class 32/64-bit RISC-V core maintained by the OpenHW Group community.
Open silicon
Ibex
A configurable 32-bit RISC-V SystemVerilog core built for embedded control applications.
Open silicon
NEORV32
A synthesizable VHDL RISC-V microcontroller SoC with processor, peripherals, bootloader, software framework, and documentation.
External index · BSD-3-ClauseCatalog date: Reviewed 2026-08-22Source for NEORV32 (opens in a new tab)↗Open silicon
OpenTitan
Open silicon root-of-trust design with hardware, firmware, verification, and integration collateral.
External index · Apache-2.0Catalog date: Reviewed 2026-08-18Source for OpenTitan (opens in a new tab)↗Open silicon
RISCV-DV
A SystemVerilog and UVM random instruction generator for RISC-V processor verification.
External index · Apache-2.0Catalog date: Reviewed 2026-08-18Source for RISCV-DV (opens in a new tab)↗Open silicon
Rocket Chip
A Chisel-based SoC generator with RISC-V cores, caches, interconnects, peripherals, and configuration infrastructure.
External index · Apache-2.0Catalog date: Reviewed 2026-08-22Source for Rocket Chip (opens in a new tab)↗Open silicon
VexRiscv
A plugin-oriented 32-bit RISC-V CPU generator designed for configurable FPGA implementations.