VLSI KoreaSearch Hub
Find public resources, specifications, standards metadata, calculators, and tapeout programs.
Public metadata and educational tools only. Example profiles and research previews without sources are excluded. Dates and source limitations stay attached to each result.
153 results to explore
Specifications
MIPI CSI-2 v4.2
Current CSI-2 version and public imaging-interface metadata linked to MIPI; member-only specification text is excluded.
Source-linked · conditions applyCatalog date: 2026-08-29Source for MIPI CSI-2 v4.2 (opens in a new tab)↗Specifications
MIPI D-PHY v3.6
Current D-PHY version and public scope metadata linked to the official MIPI overview; member-only specification text is excluded.
Source-linked · conditions applyCatalog date: 2026-08-29Source for MIPI D-PHY v3.6 (opens in a new tab)↗Tapeout & PDKs
MOSIS fabrication services
MOSIS publishes fabrication/service program information.
official program/service information public; runs subject to MOSIS confirmationCatalog date: 2026-08-26Source for MOSIS fabrication services (opens in a new tab)↗Open silicon
NEORV32
A synthesizable VHDL RISC-V microcontroller SoC with processor, peripherals, bootloader, software framework, and documentation.
External index · BSD-3-ClauseCatalog date: Reviewed 2026-08-22Source for NEORV32 (opens in a new tab)↗Open silicon
nextpnr
A portable, timing-driven FPGA place-and-route framework supporting multiple architectures and open device databases.
Open silicon
NVDLA
An open deep-learning accelerator architecture with synthesizable hardware, software stack, specifications, and integration guidance.
Tapeout & PDKs
OpenLane
Open digital RTL-to-GDSII flow associated with SKY130 enablement.
Open silicon
OpenLane 2
A configurable Python infrastructure for composing reproducible RTL-to-GDS flows around open and commercial EDA tools.
External index · Apache-2.0Catalog date: Reviewed 2026-08-22Source for OpenLane 2 (opens in a new tab)↗Specifications
OpenLane 2
Open-source ASIC-flow entity for reproducible toolchain navigation.
Open silicon
OpenPiton
A scalable manycore research platform with tiled architecture, cache coherence, synthesis, simulation, and FPGA collateral.
External index · BSD-3-ClauseCatalog date: Reviewed 2026-08-22Source for OpenPiton (opens in a new tab)↗Open silicon
OpenROAD
An integrated RTL-to-GDS application spanning floorplanning, placement, CTS, and routing.
External index · BSD-3-ClauseCatalog date: Reviewed 2026-08-18Source for OpenROAD (opens in a new tab)↗Specifications
OpenROAD
Open-source physical-design platform entity.
Open silicon
OpenTitan
Open silicon root-of-trust design with hardware, firmware, verification, and integration collateral.
External index · Apache-2.0Catalog date: Reviewed 2026-08-18Source for OpenTitan (opens in a new tab)↗Calculators
Packet Payload Efficiency
Compute payload share of named packet bytes.
Derived · educational calculationCatalog date: 2026-08-26Source for Packet Payload Efficiency (opens in a new tab)↗Specifications
PCI Express 6.x
Revision-family record; electrical and protocol details remain version-specific.
Source-linked · conditions applyCatalog date: 2026-08-28Source for PCI Express 6.x (opens in a new tab)↗Specifications
PCI Express 7.0
Public release metadata for the PCIe 7.0 base specification.
Source-linked · conditions applyCatalog date: 2026-08-28Source for PCI Express 7.0 (opens in a new tab)↗Calculators
Pipeline Latency
Convert pipeline stages and clock period into ideal latency.
Derived · educational calculationCatalog date: 2026-08-26Source for Pipeline Latency (opens in a new tab)↗Calculators
Poisson Yield
Simple Poisson yield model; not a production forecast.
Derived · educational calculationFormula and limitations on the tool pageOpen silicon
PULP AXI
Reusable SystemVerilog AXI4, AXI4-Lite, and stream components for open SoC integration and verification.
Calculators
RC Time Constant
Calculate first-order RC time constant.
Derived · educational calculationFormula and limitations on the tool page