VLSI KoreaSearch Hub
Find public resources, specifications, standards metadata, calculators, and tapeout programs.
Public metadata and educational tools only. Example profiles and research previews without sources are excluded. Dates and source limitations stay attached to each result.
30 results to explore
Open silicon
PULP AXI
Reusable SystemVerilog AXI4, AXI4-Lite, and stream components for open SoC integration and verification.
Open silicon
RISC-V Formal
A formal verification framework and interface for checking RISC-V processor implementations against ISA properties.
Open silicon
RISCV-DV
A SystemVerilog and UVM random instruction generator for RISC-V processor verification.
External index · Apache-2.0Catalog date: Reviewed 2026-08-18Source for RISCV-DV (opens in a new tab)↗Open silicon
Rocket Chip
A Chisel-based SoC generator with RISC-V cores, caches, interconnects, peripherals, and configuration infrastructure.
External index · Apache-2.0Catalog date: Reviewed 2026-08-22Source for Rocket Chip (opens in a new tab)↗Open silicon
SKY130 Open PDK
An open-source 130 nm process design kit distribution for education, research, prototyping, and open tool development.
External index · Apache-2.0Catalog date: Reviewed 2026-08-22Source for SKY130 Open PDK (opens in a new tab)↗Open silicon
SymbiYosys
A front end for reproducible safety, liveness, cover, and equivalence flows using open formal engines.
Open silicon
Verible
A suite of SystemVerilog developer tools including parser, linter, formatter, language server, and syntax utilities.
External index · Apache-2.0Catalog date: Reviewed 2026-08-22Source for Verible (opens in a new tab)↗Open silicon
Verilator
A fast SystemVerilog compiler, simulator, lint engine, and coverage tool for software-driven hardware verification.
External index · LGPL-3.0-only OR Artistic-2.0Catalog date: Reviewed 2026-08-22Source for Verilator (opens in a new tab)↗Open silicon
VexRiscv
A plugin-oriented 32-bit RISC-V CPU generator designed for configurable FPGA implementations.
Open silicon
Yosys
An open RTL synthesis framework extensible through scripts, frontends, backends, and C++ passes.