Expected failure, exit 1
VCD info: dumpfile wave.vcd opened for output.
FATAL: tb.sv:20: Expected negative-control failure
       Time: 196000  Scope: tb

Missing-top compile exit 1
error: Unable to find the root module "missing_top" in the Verilog source.
     : Perhaps ``-s missing_top'' is incorrect?
1 error(s) during elaboration.