VLSI Koreaibex pinned upstream documentation
Ibex README describes Yosys area evaluation using its basic synthesis flow and latch-based register file. No area figures are republished.
- Published
- Not stated
- Retrieved
- 2026-10-13
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FuseSoC4 entities and 3 documented connections shown.
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Select a connection for its evidenceRelationships & evidence (3)
| Subject | Relationship | Object | Status | Evidence |
|---|---|---|---|---|
| Ibex | Yosys | SUPPORTEDValidity dates not established | Why are these connected?Ibex README describes Yosys area evaluation using its basic synthesis flow and latch-based register file. No area figures are republished. | |
| Ibex | Verilator | SUPPORTEDValidity dates not established | Why are these connected?Ibex Simple System simulation example requires Verilator; this is a specific example, not a guarantee for every Ibex configuration. ibex pinned upstream documentationIbex Simple System simulation example requires Verilator; this is a specific example, not a guarantee for every Ibex configuration.
| |
| Ibex | FuseSoC | SUPPORTEDValidity dates not established | Why are these connected?The Simple System simulator build described here is driven by FuseSoC. ibex pinned upstream documentationThe Simple System simulator build described here is driven by FuseSoC.
|
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