A source-reported date is a historical snapshot. Unknown validity is excluded when a date is selected. “Known to VLSI” uses the end of that UTC day. This entity’s heading uses its current label.
Ibex README describes Yosys area evaluation using its basic synthesis flow and latch-based register file. No area figures are republished.
Validity dates not established
Why are these connected? Inspect evidence and history
Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
The source establishes a scoped registry listing or documented integration at its observed revision. Publication, Git commit, retrieval and shuttle labels do not establish a relationship validity period.
Official ibex repository · Tier A · Primary source · supports
Evidence summary: Ibex README describes Yosys area evaluation using its basic synthesis flow and latch-based register file. No area figures are republished.
Published: not stated · Retrieved: 2026-10-13 · Extraction: deterministic-adapter
Only original factual paraphrases, selected registry identity/revision/module metadata, source-byte hash and links are published. Complete source documents are not redistributed. Included code, libraries, PDKs and manufacturing use retain separate terms.
First observed by VLSI: 2026-10-14T00:04:17.557Z. No independent human verification recorded.
Review: Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.
Ibex Simple System simulation example requires Verilator; this is a specific example, not a guarantee for every Ibex configuration.
Validity dates not established
Why are these connected? Inspect evidence and history
Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
The source establishes a scoped registry listing or documented integration at its observed revision. Publication, Git commit, retrieval and shuttle labels do not establish a relationship validity period.
Official ibex repository · Tier A · Primary source · supports
Evidence summary: Ibex Simple System simulation example requires Verilator; this is a specific example, not a guarantee for every Ibex configuration.
Location: Simple System / Prerequisites
Published: not stated · Retrieved: 2026-10-13 · Extraction: deterministic-adapter
Only original factual paraphrases, selected registry identity/revision/module metadata, source-byte hash and links are published. Complete source documents are not redistributed. Included code, libraries, PDKs and manufacturing use retain separate terms.
First observed by VLSI: 2026-10-14T00:04:17.557Z. No independent human verification recorded.
Review: Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.
The Simple System simulator build described here is driven by FuseSoC.
Validity dates not established
Why are these connected? Inspect evidence and history
Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
The source establishes a scoped registry listing or documented integration at its observed revision. Publication, Git commit, retrieval and shuttle labels do not establish a relationship validity period.
Official ibex repository · Tier A · Primary source · supports
Evidence summary: The Simple System simulator build described here is driven by FuseSoC.
Location: Simple System / Building Simulation
Published: not stated · Retrieved: 2026-10-13 · Extraction: deterministic-adapter
Only original factual paraphrases, selected registry identity/revision/module metadata, source-byte hash and links are published. Complete source documents are not redistributed. Included code, libraries, PDKs and manufacturing use retain separate terms.
First observed by VLSI: 2026-10-14T00:04:17.557Z. No independent human verification recorded.
Review: Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.
VLSI Hub / Knowledge