Skip to main content
VLSI Korea

Auditable claim record

Ibex · uses tool

Yosys · SUPPORTED

urn:vlsi:claim:4ed1cb842d4e3e0fa36e5d8c1f909c53ab4c85adc94ee072d5583df293127f4d

Ibex README describes Yosys area evaluation using its basic synthesis flow and latch-based register file. No area figures are republished.

Back to Ibex → · Complete history as JSON · JSON-LD

Evidence

ibex pinned upstream documentation ↗

Ibex README describes Yosys area evaluation using its basic synthesis flow and latch-based register file. No area figures are republished.

Official ibex repository · README / Configuration / Yosys synthesis notes · supports

Published date unknown · Retrieved 2026-10-13T23:58:55.154Z

urn:vlsi:evidence:f89ae265db8983df71030718ae8f439db8d41af44870314526af9637d8504b95

Assessment history

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
RevisionRecorded at (UTC)StatusValidityReviewer & reason
12026-10-14T00:04:17.557ZSUPPORTEDunknown
unknown
checked-catalog-source-adapter (adapter)

Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.