Skip to main content
VLSI Korea

Semiconductor graph

Verilator
Methods ↗

2 entities and 1 documented connections shown.

Connections

2 entities · 1 claims
100%

Drag the map or use pan buttons to move. Tab to a node or connection and press Enter to inspect its evidence. Arrows follow the actual claim direction.

STARTING ENTITYDIRECT CONNECTIONSIncludes · SUPPORTEDIncludesOSS CAD Suite · open source projectOPEN SOURCE PROJECTOSS CAD SuiteVerilator · eda toolEDA TOOLSTARTVerilator
CompanyChip / productTechnologyPlace / facility
Select a connection for its evidence
Relationships & evidence (1)
Every displayed connection is a scoped claim. Arrows follow subject to object.
SubjectRelationshipObjectStatusEvidence
OSS CAD SuiteVerilatorSUPPORTEDValidity dates not established
Why are these connected?

Listed distribution component at the pinned README revision; availability depends on the upstream release and supported platform. Component license is not replaced by the distribution license.

OSS CAD Suite README

YosysHQ · Tier A · Primary source · supports

The OSS CAD Suite README lists Verilator among its distribution components.

Location: Pinned README.md line 81: Verilog/SystemVerilog simulation

Published
Not stated
Retrieved
2026-10-13

Store factual paraphrases, metadata, source-byte SHA-256 and pinned document link only. Source bytes were fetched for this review but are not retained or redistributed. Repository and component licenses remain separate. Commit date is not document publication or relationship validity.

Full claim history →
Find an evidence path

Find a documented path

From Verilator · up to two relationship steps.

A path retains its original claims. Shared technology does not establish a supply contract.

2 nodes · 1 claims
Scope

Relationships may describe different dates. A path does not establish simultaneous activity. Bounded source-backed collection. Missing or filtered connections do not establish absence. Supported does not mean independently verified.