Auditable claim record

OSS CAD Suite · includes

Verilator · SUPPORTED

urn:vlsi:claim:52032b74c69138e44fe78fc959a27f3937a5882536a7575856633d59c0a66bb4

Listed distribution component at the pinned README revision; availability depends on the upstream release and supported platform. Component license is not replaced by the distribution license.

Back to OSS CAD Suite → · Complete history as JSON · JSON-LD

Evidence

OSS CAD Suite README ↗

The OSS CAD Suite README lists Verilator among its distribution components.

YosysHQ · Pinned README.md line 81: Verilog/SystemVerilog simulation · supports

Published date unknown · Retrieved 2026-10-13T16:27:12.704Z

urn:vlsi:evidence:e9add917ed4264c8268db6d67a3441a285d87121c337b0ff1091ddbfd6202483

Assessment history

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
Revision	Recorded at (UTC)	Status	Validity	Reviewer & reason
1	2026-10-13T16:28:40.236Z	SUPPORTED	unknown unknown	pinned-upstream-document-review (agent) Evidence ingested by pinned-upstream-readme-review/1.0.0. Documented scope only. No arbitrary-version interoperability, foundry signoff, fabrication, measurement or production qualification is established. Individual components retain their own licenses.