From architecture to layout

Describe what should happen.

Architecture sets goals. RTL describes behavior at register-transfer level, and synthesis maps logic into cells under timing, power and area constraints. Verification starts early and continues throughout the flow.

Give logic a physical home.

Floorplanning organizes blocks. Placement arranges cells, clock-tree synthesis distributes the clock, and routing connects pins with wires. Physical distance now matters to the design.

Check. Revise. Check again.

Timing and physical checks send engineers back to earlier decisions. Once signoff goals are met, tape-out delivers the layout toward mask preparation. Materials and design meet in fabrication—not in a single chronological production line.

Technical context

In parallel with material preparation, engineers describe intended behavior in RTL and turn it into a manufacturable physical layout. Logic is synthesized, blocks and cells are arranged, clocks and wires are built, and checks repeatedly test whether the design will meet its goals. The result sent toward masks is the product of iteration, not a single automatic conversion.

• RTL and constraints are inputs to synthesis; synthesis optimizes implementation goals such as timing, area, power and test.
• Physical implementation includes floorplanning, placement, clock-tree synthesis and routing, with estimates and optimization feeding across stages.
• Signoff-quality timing and other checks guide closure; a convergent flow reduces rework but does not eliminate iteration before tapeout.

Sources

Design Compiler: Timing, Area, Power, & Test Optimization ↗ · Synopsys

What Is Physical Synthesis? ↗ · Synopsys