VLSI KoreaSILICON COMPATIBILITY
Follow the evidence between projects.
Each connection describes a specific documented dependency or integration. It records the source revision and scope. A documented connection does not imply an independently tested combination, transitive compatibility, or tapeout readiness.
6 documented connections. Absence of a connection means missing evidence.
| Source → target | Relationship / evidence | Scope |
|---|---|---|
| Ibex Yosys | used_in_flow upstream-documented | Ibex README describes Yosys area evaluation using its basic synthesis flow and latch-based register file. No area figures are republished. Inspect evidence → |
| OpenLane 2 Yosys | depends_on upstream-documented | OpenLane describes Yosys among its infrastructure components. Inspect evidence → |
| OpenROAD Yosys | integrates_with upstream-documented | The OpenROAD README describes an ORFS flow whose synthesis stage uses Yosys. The OpenROAD application itself is not the complete ORFS flow. Inspect evidence → |
| SymbiYosys Yosys | depends_on upstream-documented | SymbiYosys describes itself as a front-end for Yosys-based formal verification flows; solver and frontend selection affect applicability. Inspect evidence → |
| Yosys SymbiYosys | integrates_with upstream-documented | The Yosys README links SBY as its formal verification front-end; installed solvers and supported syntax remain separate requirements. Inspect evidence → |
| Yosys Verilator | integrates_with upstream-documented | The README recommends a separate Verilator lint check because the read_verilog command does not perform syntax checking. Inspect evidence → |