VLSI KoreaSILICON COMPATIBILITY
Follow the evidence between projects.
Each connection describes a specific documented dependency or integration. It records the source revision and scope. A documented connection does not imply an independently tested combination, transitive compatibility, or tapeout readiness.
3 documented connections. Absence of a connection means missing evidence.
| Source → target | Relationship / evidence | Scope |
|---|---|---|
| Ibex FuseSoC | depends_on upstream-documented | The Simple System simulator build described here is driven by FuseSoC. Inspect evidence → |
| Ibex Verilator | requires upstream-documented | Ibex Simple System simulation example requires Verilator; this is a specific example, not a guarantee for every Ibex configuration. Inspect evidence → |
| Ibex Yosys | used_in_flow upstream-documented | Ibex README describes Yosys area evaluation using its basic synthesis flow and latch-based register file. No area figures are republished. Inspect evidence → |