Knowledge / memory technology
HBM3 Canonical entity with source-backed relationships and retained history.
urn:vlsi:entity:460cdac2-4aec-4446-9d53-2dbafebb22a7
A source-reported date is a historical snapshot. Unknown validity is excluded when a date is selected. “Known to VLSI” uses the end of that UTC day. This entity’s heading uses its current label.
Recorded relationships SUPPORTED 1 evidence record · Revision 1
Variant-specific: NVIDIA also describes PCIe H100 configurations with HBM2e.
Source-reported snapshot: 2022-03-22
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
NVIDIA Technical Blog · Tier A · Primary source · supports
Evidence summary: NVIDIA specifies H100 SXM5 with 80 GB HBM3 across five HBM3 stacks.
Location: H100 SXM5 implementation
Published: 2022-03-22 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: Evidence ingested by curated-primary-sources/1.0.0. Variant-specific: NVIDIA also describes PCIe H100 configurations with HBM2e.
Full claim history → SUPPORTED 1 evidence record · Revision 1
No memory-chip vendor is asserted.
Source-reported snapshot: 2023-12-06
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
AMD · Tier A · Primary source · supports
Evidence summary: AMD specifies MI300X with 192 GB of HBM3 memory.
Location: lines 463-467 / AMD Instinct MI300X
Published: 2023-12-06 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: Evidence ingested by curated-primary-sources/1.0.0. No memory-chip vendor is asserted.
Full claim history → SUPPORTED 1 evidence record · Revision 1
No memory-chip vendor is asserted.
Source-reported snapshot: 2023-12-06
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
AMD · Tier A · Primary source · supports
Evidence summary: AMD specifies MI300A with 128 GB of HBM3 memory.
Location: lines 470-474 / AMD Instinct MI300A
Published: 2023-12-06 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: Evidence ingested by curated-primary-sources/1.0.0. No memory-chip vendor is asserted.
Full claim history → Connections through a shared technology show an ecosystem association. They do not establish a supply contract, exclusive dependency or supplier share. Inspect coverage gaps → 
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