Knowledge / product
AMD Instinct MI300A Canonical entity with source-backed relationships and retained history.
urn:vlsi:entity:ea0b560b-a2c1-408f-8d9d-27df9e1d4082
A source-reported date is a historical snapshot. Unknown validity is excluded when a date is selected. “Known to VLSI” uses the end of that UTC day. This entity’s heading uses its current label.
Recorded relationships SUPPORTED 1 evidence record · Revision 1
This is a heterogeneous APU claim, not a relationship to an external CPU supplier.
Source-reported snapshot: 2023-12-06
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
AMD · Tier A · Primary source · supports
Evidence summary: AMD says MI300A combines Zen 4 x86 CPU cores with CDNA 3 GPU cores.
Location: lines 470-474 / AMD Instinct MI300A
Published: 2023-12-06 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: Evidence ingested by curated-primary-sources/1.0.0. This is a heterogeneous APU claim, not a relationship to an external CPU supplier.
Full claim history → SUPPORTED 1 evidence record · Revision 1
This claim covers the GPU-side architecture only.
Source-reported snapshot: 2023-12-06
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
AMD · Tier A · Primary source · supports
Evidence summary: AMD says MI300A combines CDNA 3 GPU cores with Zen 4 x86 CPU cores.
Location: lines 470-474 / AMD Instinct MI300A
Published: 2023-12-06 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: Evidence ingested by curated-primary-sources/1.0.0. This claim covers the GPU-side architecture only.
Full claim history → SUPPORTED 1 evidence record · Revision 1
No external packaging service provider is asserted.
Source-reported snapshot: 2023-12-06
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
AMD · Tier A · Primary source · supports
Evidence summary: AMD says MI300A leverages 3D packaging and fourth-generation AMD Infinity Architecture.
Location: lines 470-471 / AMD Instinct MI300A
Published: 2023-12-06 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: Evidence ingested by curated-primary-sources/1.0.0. No external packaging service provider is asserted.
Full claim history → SUPPORTED 1 evidence record · Revision 1
No memory-chip vendor is asserted.
Source-reported snapshot: 2023-12-06
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
AMD · Tier A · Primary source · supports
Evidence summary: AMD specifies MI300A with 128 GB of HBM3 memory.
Location: lines 470-474 / AMD Instinct MI300A
Published: 2023-12-06 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: Evidence ingested by curated-primary-sources/1.0.0. No memory-chip vendor is asserted.
Full claim history → Connections through a shared technology show an ecosystem association. They do not establish a supply contract, exclusive dependency or supplier share. Inspect coverage gaps → 
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