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VLSI Korea

SILICON COMPATIBILITY

Follow the evidence between projects.

Each connection describes a specific documented dependency or integration. It records the source revision and scope. A documented connection does not imply an independently tested combination, transitive compatibility, or tapeout readiness.

14 documented connections. Absence of a connection means missing evidence.

Bounded relationship view · up to 12 connections per page
Source → targetRelationship / evidenceScope
Yosys
SymbiYosys
integrates_with
upstream-documented
The Yosys README links SBY as its formal verification front-end; installed solvers and supported syntax remain separate requirements.
Inspect evidence →
Yosys
Verilator
integrates_with
upstream-documented
The README recommends a separate Verilator lint check because the read_verilog command does not perform syntax checking.
Inspect evidence →