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RTL / SUBMITTED DESIGN SOURCE-LINKED RECORD

schoeberl /

Wildcat RISC-V

Tiny Tapeout IHP 25a design submission. Project metadata identifies its implementation as Chisel; source and license are linked at the submitted revision.

Tiny Tapeout · Submitted design · Indexed from author-supplied metadata

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CLONE UPSTREAMgit clone https://github.com/schoeberl/tt10-wildcat.git

SILICON PASSPORT

Engineering facts, with their evidence.

Source checks, licensing, documentation, execution and silicon results are distinct claims.

Source linkedLicense check not recordedHub run not recorded

This legacy resource retains its original catalog observation. A pinned fresh source/ license check has not been recorded yet.

Documented engineering specifications
FactValueEvidence
No deep engineering profile has been reviewed. The catalog's language, target and toolchain labels are historical metadata.

Documented dependencies and compatibility

No evidence-backed relationship is recorded for this resource. Integration assumptions remain untested.

Remaining unknowns

  • No independently retained Hub build, simulation or silicon result is attached.
  • Tool-version compatibility and implementation constraints require review before reuse.
01 / FILES & REVISIONS

Files from the source.
History from the source.

This release does not mirror repository files or invent a local file listing. It links only to known official paths.

PINNED REVISION
c5cb86899d2494c1bfb42fbc3420ff58c397f085

This record uses the revision listed in the official submission manifest. Hub has not built or tested this revision.

02 / PROVENANCE & EVIDENCE

Inspect the evidence
before the claim.

These fields are official upstream references and catalog observations—not an internal Hub certification.

  1. 01
  2. 02
  3. 03
  4. 04
    CATALOG REVIEWRegistry indexed 2026-09-26
  5. 05
    LICENSE CONTENT CHECKObserved 2026-09-26 ↗SHA-256: c71d239df91726fc519c6eb72d318ec65820627232b2f796219e87dcf35d0ab4
  6. 06
03 / REPRODUCIBLE RUNS

No Hub run is attached yet.

We do not invent measurements or relabel upstream results as Hub executions.

RUN STATUS / EMPTYNO HUB RUNS

VLSI Hub has not yet performed and recorded a build, simulation, synthesis, P&R, FPGA, or benchmark run for Wildcat RISC-V.

REQUIRED FOR A FUTURE RUN
  1. 01Pinned source revision
  2. 02Tool and environment versions
  3. 03Commands, constraints, and seed
  4. 04Logs and result artifacts
04 / COMMUNITY

Route discussion and contribution
to the upstream.

This release does not mirror or aggregate issues, pull requests, or participant counts.