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Browse github.com/YosysHQ/icestormYosysHQ /
An open-source tooling project for Lattice iCE40 FPGA bitstreams.
git clone https://github.com/YosysHQ/icestorm.gitSource checks, licensing, documentation, execution and silicon results are distinct claims.
This legacy resource retains its original catalog observation. A pinned fresh source/ license check has not been recorded yet.
| Fact | Value | Evidence |
|---|---|---|
| No deep engineering profile has been reviewed. The catalog's language, target and toolchain labels are historical metadata. | ||
No evidence-backed relationship is recorded for this resource. Integration assumptions remain untested.
This release does not mirror repository files or invent a local file listing. It links only to known official paths.
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Browse github.com/YosysHQ/icestormThis is the license-file path recorded by the catalog. Review the original text for its exact scope.
Read ISC sourceSee upstream documentation for releases and maintenance status.
Inspect activity evidenceThis catalog entry does not name a specific tag or commit SHA. Pin a revision from the official repository before attempting reproduction.
These fields are official upstream references and catalog observations—not an internal Hub certification.
We do not invent measurements or relabel upstream results as Hub executions.
VLSI Hub has not yet performed and recorded a build, simulation, synthesis, P&R, FPGA, or benchmark run for Project IceStorm.
This release does not mirror or aggregate issues, pull requests, or participant counts.
Project IceStorm canonical record · Explore the graph →
The official OSS CAD Suite manifest lists this component. Platform availability, target versions and individual component licenses remain separate; inclusion is not universal interoperability.
OSS CAD Suite pinned component manifest ↗ · Retrieved 2026-10-13
Claim history →Documented tool use or inclusion does not establish version compatibility or fabrication qualification.