Auditable claim record

Semana UCU Verilog · listed in shuttle

Tiny Tapeout 9 · SUPPORTED

urn:vlsi:claim:87c67be68d2716193e57857accb646fd4ec8cf79ab2307c62023e246b35dd2e5

Official registry lists this repository, submitted revision and module. The listing does not establish fabrication, manufacture, validation or measured results.

Back to Semana UCU Verilog → · Complete history as JSON · JSON-LD

Evidence

Tiny Tapeout 9 official shuttle registry ↗

The Tiny Tapeout 9 registry lists this repository at submitted revision fa41d2c56a9a5ff5c3d8bd7276cc50e3ccce0cc2, under module tt_um_wokwi_411379488132926465.

Tiny Tapeout official registry · projects[196]: repository, commit and macro · supports

Published date unknown · Retrieved 2026-10-13T23:58:53.989Z

urn:vlsi:evidence:8669b1b30882622d8c85309bf6c84499ef456289f177127ad44879d9941b68ef

Assessment history

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
Revision	Recorded at (UTC)	Status	Validity	Reviewer & reason
1	2026-10-14T00:04:16.868Z	SUPPORTED	unknown unknown	checked-catalog-source-adapter (adapter) Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.