Auditable claim record

Verilog OR-Gate · listed in shuttle

Tiny Tapeout IHP 25b · SUPPORTED

urn:vlsi:claim:5267fd8aacdbe06b201b7d87a8517c26711898f2343b16b1a77d4584b1f044a3

Official registry lists this repository, submitted revision and module. The listing does not establish fabrication, manufacture, validation or measured results.

Back to Verilog OR-Gate → · Complete history as JSON · JSON-LD

Evidence

Tiny Tapeout IHP 25b official shuttle registry ↗

The Tiny Tapeout IHP 25b registry lists this repository at submitted revision 4c1b72e2b111bc2ebf6e3ce4bb9b3528d741bb0a, under module tt_um_test_chip_pius.

Tiny Tapeout official registry · projects[72]: repository, commit and macro · supports

Published date unknown · Retrieved 2026-10-13T23:58:54.682Z

urn:vlsi:evidence:8d84612c03d88f8d8e6177ec85b29e8d05f348253c5d4d7d8cd19310f7be863e

Assessment history

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
Revision	Recorded at (UTC)	Status	Validity	Reviewer & reason
1	2026-10-14T00:04:17.137Z	SUPPORTED	unknown unknown	checked-catalog-source-adapter (adapter) Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.