Knowledge / process
custom-built TSMC 4NP Canonical entity with source-backed relationships and retained history.
urn:vlsi:entity:8fe8864b-559a-4a04-8795-1cbe8bbe5429
A source-reported date is a historical snapshot. Unknown validity is excluded when a date is selected. “Known to VLSI” uses the end of that UTC day. This entity’s heading uses its current label.
Recorded relationships RETRACTED 1 evidence record · Revision 2
Named TSMC process in the cited product specification.
Source-reported snapshot: 2024-03-18
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
NVIDIA Newsroom · Tier A · Primary source · supports
Evidence summary: NVIDIA identifies the named process as a TSMC manufacturing process.
Location: line 72 / World's Most Powerful Chip
Published: 2024-03-18 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: A product announcement names the custom process but does not establish a general foundry offering. Retract this inferred corporate relation.
Full claim history → SUPPORTED 1 evidence record · Revision 1
Evidence names the process and TSMC; it does not identify a fab location.
Source-reported snapshot: 2024-03-18
Inspect evidence, confidence and history Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
Dated source-reported snapshot. Publication date is not an inferred manufacturing start, contract start or legal-close date.
NVIDIA Newsroom · Tier A · Primary source · supports
Evidence summary: NVIDIA states Blackwell-architecture GPUs are manufactured using a custom-built 4NP TSMC process.
Location: line 72 / World's Most Powerful Chip
Published: 2024-03-18 · Retrieved: 2026-09-08 · Extraction: manual-source-review
Store factual paraphrase, metadata and link only. No source document redistribution or inferred license; no source bytes retained.
First observed by VLSI: 2026-09-08T15:57:21.457Z. No independent human verification recorded.
Review: Evidence ingested by curated-primary-sources/1.0.0. Evidence names the process and TSMC; it does not identify a fab location.
Full claim history → Connections through a shared technology show an ecosystem association. They do not establish a supply contract, exclusive dependency or supplier share. Inspect coverage gaps → 
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