A source-reported date is a historical snapshot. Unknown validity is excluded when a date is selected. “Known to VLSI” uses the end of that UTC day. This entity’s heading uses its current label.
OpenLane describes Yosys among its infrastructure components.
Validity dates not established
Why are these connected? Inspect evidence and history
Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
The source establishes a scoped registry listing or documented integration at its observed revision. Publication, Git commit, retrieval and shuttle labels do not establish a relationship validity period.
Official openlane2 repository · Tier A · Primary source · supports
Evidence summary: OpenLane describes Yosys among its infrastructure components.
Location: Readme / ASIC infrastructure components
Published: not stated · Retrieved: 2026-10-13 · Extraction: deterministic-adapter
Only original factual paraphrases, selected registry identity/revision/module metadata, source-byte hash and links are published. Complete source documents are not redistributed. Included code, libraries, PDKs and manufacturing use retain separate terms.
First observed by VLSI: 2026-10-14T00:04:17.557Z. No independent human verification recorded.
Review: Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.
OpenLane describes OpenROAD among its infrastructure components.
Validity dates not established
Why are these connected? Inspect evidence and history
Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
The source establishes a scoped registry listing or documented integration at its observed revision. Publication, Git commit, retrieval and shuttle labels do not establish a relationship validity period.
Official openlane2 repository · Tier A · Primary source · supports
Evidence summary: OpenLane describes OpenROAD among its infrastructure components.
Location: Readme / ASIC infrastructure components
Published: not stated · Retrieved: 2026-10-13 · Extraction: deterministic-adapter
Only original factual paraphrases, selected registry identity/revision/module metadata, source-byte hash and links are published. Complete source documents are not redistributed. Included code, libraries, PDKs and manufacturing use retain separate terms.
First observed by VLSI: 2026-10-14T00:04:17.557Z. No independent human verification recorded.
Review: Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.
OpenLane describes KLayout among its infrastructure components.
Validity dates not established
Why are these connected? Inspect evidence and history
Evidence index 85/100 · A rule-based index, not the probability this claim is true. 1 independent source origin(s).
The source establishes a scoped registry listing or documented integration at its observed revision. Publication, Git commit, retrieval and shuttle labels do not establish a relationship validity period.
Official openlane2 repository · Tier A · Primary source · supports
Evidence summary: OpenLane describes KLayout among its infrastructure components.
Location: Readme / ASIC infrastructure components
Published: not stated · Retrieved: 2026-10-13 · Extraction: deterministic-adapter
Only original factual paraphrases, selected registry identity/revision/module metadata, source-byte hash and links are published. Complete source documents are not redistributed. Included code, libraries, PDKs and manufacturing use retain separate terms.
First observed by VLSI: 2026-10-14T00:04:17.557Z. No independent human verification recorded.
Review: Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.
VLSI Hub / Knowledge