Auditable claim record

OpenROAD Flow Scripts · uses tool

Yosys · SUPPORTED

urn:vlsi:claim:e635636e4936adea345ab2f2bae7a5fcdcc7f101108b1bb04190ae6ca42ff475

Yosys is documented for the synthesis stage of OpenROAD Flow Scripts at this source revision.

Evidence

The ORFS flow diagram assigns logic synthesis to Yosys.

The OpenROAD Project · Pinned README.md line 19: RTL synthesis · supports

Published date unknown · Retrieved 2026-10-13T16:27:12.691Z

urn:vlsi:evidence:a035c9ad19d33ee1bf9e2110f13473cc54a04afacb271934c8af5ac5f42050fd

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
Revision	Recorded at (UTC)	Status	Validity	Reviewer & reason
1	2026-10-13T16:28:40.236Z	SUPPORTED	unknown unknown	pinned-upstream-document-review (agent) Evidence ingested by pinned-upstream-readme-review/1.0.0. Documented scope only. No arbitrary-version interoperability, foundry signoff, fabrication, measurement or production qualification is established. Individual components retain their own licenses.