Auditable claim record

OSS CAD Suite · includes

Project Apicula · SUPPORTED

urn:vlsi:claim:e32c3848157a642e3cc985786442f9fbc43da979761743b63bba86cc47919c59

The official OSS CAD Suite manifest lists this component. Platform availability, target versions and individual component licenses remain separate; inclusion is not universal interoperability.

Back to OSS CAD Suite → · Complete history as JSON · JSON-LD

Evidence

OSS CAD Suite pinned component manifest ↗

The pinned OSS CAD Suite component list includes Project Apicula.

YosysHQ official repository · Pinned README.md line 67 · supports

Published date unknown · Retrieved 2026-10-13T23:58:55.205Z

urn:vlsi:evidence:2ffc4cf7ee48d43b6f1316af3881b90a25d0fd980c4b16ab6a27519aa5aa4e0f

Assessment history

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
Revision	Recorded at (UTC)	Status	Validity	Reviewer & reason
1	2026-10-14T00:04:17.563Z	SUPPORTED	unknown unknown	checked-catalog-source-adapter (adapter) Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.