Auditable claim record

Verilog based clock to 7-segment counter · listed in shuttle

Tiny Tapeout IHP 25a · SUPPORTED

urn:vlsi:claim:cfb5a4fa307cb330e966591dc15053fbb590048eff50694e29de0b3ee83328eb

Official registry lists this repository, submitted revision and module. The listing does not establish fabrication, manufacture, validation or measured results.

Back to Verilog based clock to 7-segment counter → · Complete history as JSON · JSON-LD

Evidence

Tiny Tapeout IHP 25a official shuttle registry ↗

The Tiny Tapeout IHP 25a registry lists this repository at submitted revision 0de52d2378ac13825fd5e42c900714d041d4c274, under module tt_um_enjens.

Tiny Tapeout official registry · projects[259]: repository, commit and macro · supports

Published date unknown · Retrieved 2026-10-13T23:58:54.646Z

urn:vlsi:evidence:bc58147c05549e822beea70450eb27c7a8fd229ab7753e815330abaffbf8bf0b

Assessment history

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
Revision	Recorded at (UTC)	Status	Validity	Reviewer & reason
1	2026-10-14T00:04:17.112Z	SUPPORTED	unknown unknown	checked-catalog-source-adapter (adapter) Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.