Auditable claim record

Delay Line Time Multiplexed NAND Gate · listed in shuttle

Tiny Tapeout 7 · SUPPORTED

urn:vlsi:claim:4eb09fbefe5dfb644eb988d318aa026c46d43f47d6a2dae002cdbc98ec850891

Official registry lists this repository, submitted revision and module. The listing does not establish fabrication, manufacture, validation or measured results.

Back to Delay Line Time Multiplexed NAND Gate → · Complete history as JSON · JSON-LD

Evidence

Tiny Tapeout 7 official shuttle registry ↗

The Tiny Tapeout 7 registry lists this repository at submitted revision e6e74ac1af72774bf6ff615e307de2f361247130, under module tt_um_delay_line_tmng.

Tiny Tapeout official registry · projects[73]: repository, commit and macro · supports

Published date unknown · Retrieved 2026-10-13T23:58:53.982Z

urn:vlsi:evidence:d4e1da7ff4c0b358b0adb3b160292b4c089cb23b16a8cc9c01d872a77719e532

Assessment history

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
Revision	Recorded at (UTC)	Status	Validity	Reviewer & reason
1	2026-10-14T00:04:16.781Z	SUPPORTED	unknown unknown	checked-catalog-source-adapter (adapter) Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.