Auditable claim record

Yosys · documents use of

Verilator · SUPPORTED

urn:vlsi:claim:37410606f0000b31c983f5bda926595e89ee1c3c4cf4bb10ed4cf03f9f4dc936

The README recommends a separate Verilator lint check because the read_verilog command does not perform syntax checking.

Evidence

The README recommends a separate Verilator lint check because the read_verilog command does not perform syntax checking.

Official yosys repository · README / Additional information · supports

Published date unknown · Retrieved 2026-10-13T23:58:55.163Z

urn:vlsi:evidence:e63920e9241cf8b9ea60a14eb30288cfe075fce84ba1f2b0df823451a7d4055d

New assessments preserve earlier records. A correction changes the current interpretation without rewriting what VLSI knew before it.

Recorded assessments, oldest first
Revision	Recorded at (UTC)	Status	Validity	Reviewer & reason
1	2026-10-14T00:04:17.557Z	SUPPORTED	unknown unknown	checked-catalog-source-adapter (adapter) Evidence ingested by official-registry-and-pinned-documents/1.0.0. Explicit upstream evidence only. No fabrication, validation, successful tapeout, measured performance, arbitrary-version interoperability or production qualification is inferred.