{"apiVersion":"1.0","data":{"id":"tt-b664b0a7a556","name":"Verilog Meetup Template Project Example","owner":"yuri-panchul","source":"https://github.com/yuri-panchul/ttsky-verilog-calpoly-slo-final","licenseSource":"https://github.com/yuri-panchul/ttsky-verilog-calpoly-slo-final/blob/115306a583013661c86ab6f46dc1b0b425e6c470/LICENSE","license":"Apache-2.0","description":"Tiny Tapeout SKY 25b design submission. Project metadata identifies its implementation as SystemVerilog; source and license are linked at the submitted revision.","domains":["Digital"],"kind":"IP/Design","tasks":["Architecture"],"language":"SystemVerilog","target":"Tiny Tapeout submitted design","toolchain":"See the pinned project documentation","tags":["Tiny Tapeout","Submitted design","Tiny Tapeout SKY 25b","Digital interface"],"discoverySources":["https://tinytapeout.github.io/tinytapeout-sky-25b/shuttle_index.json"],"evidence":{"readmeUrl":"https://github.com/yuri-panchul/ttsky-verilog-calpoly-slo-final/blob/115306a583013661c86ab6f46dc1b0b425e6c470/info.yaml","licenseUrl":"https://raw.githubusercontent.com/yuri-panchul/ttsky-verilog-calpoly-slo-final/115306a583013661c86ab6f46dc1b0b425e6c470/LICENSE","licenseSha256":"c71d239df91726fc519c6eb72d318ec65820627232b2f796219e87dcf35d0ab4","checkedAt":"2026-09-26T19:37:38.453890+00:00","notes":"Registry metadata import. License text matched a recognized root grant at the submitted revision; third-party files may have separate terms. Source metadata is author supplied. No build, fabrication, or measurement claim is made by Hub."},"sourceRevision":"115306a583013661c86ab6f46dc1b0b425e6c470","registry":"Tiny Tapeout","reviewMethod":"registry_metadata","metadataSha256":"62bd8bc9998b8efb1360642dd1a445b0740181f2d685dc9371b200da17575fe4","aliases":["tt_um_verilog_meetup_template_project_example","ttsky-verilog-calpoly-slo-final"],"type":"Submitted Design","stage":"RTL","sourceLabel":"github.com/yuri-panchul/ttsky-verilog-calpoly-slo-final","status":"External index","activitySource":"https://github.com/yuri-panchul/ttsky-verilog-calpoly-slo-final/blob/115306a583013661c86ab6f46dc1b0b425e6c470/info.yaml","activity":"See upstream documentation for releases and maintenance status.","cataloged":"Registry indexed 2026-09-26","licenseScope":"Registry metadata import. License text matched a recognized root grant at the submitted revision; third-party files may have separate terms. Source metadata is author supplied. No build, fabrication, or measurement claim is made by Hub.","accent":"blue","glyph":"VE","passport":null,"links":{"self":"/api/v1/resources/tt-b664b0a7a556","html":"/repo/tt-b664b0a7a556","evidence":"/api/v1/resources/tt-b664b0a7a556/evidence","runs":"/api/v1/resources/tt-b664b0a7a556/runs"}},"attribution":{"catalog":"https://hub.vlsi.kr","methodology":"https://hub.vlsi.kr/methodology","note":"Source documentation, license evidence, Hub reproduction and silicon reports are separate claims."}}