{"apiVersion":"1.0","data":{"id":"tt-77a25fab3b05","name":"Michaels Tiny Tapeout ALU","owner":"MichaelMcCulloch1","source":"https://github.com/MichaelMcCulloch1/tt09-verilog-Michael-ALU","licenseSource":"https://github.com/MichaelMcCulloch1/tt09-verilog-Michael-ALU/blob/0648e618dedc0d3d33b031926681e6615c1c4658/LICENSE","license":"Apache-2.0","description":"Tiny Tapeout 9 design submission. Project metadata identifies its implementation as Verilog; source and license are linked at the submitted revision.","domains":["Digital"],"kind":"IP/Design","tasks":["Architecture"],"language":"Verilog","target":"Tiny Tapeout submitted design","toolchain":"See the pinned project documentation","tags":["Tiny Tapeout","Submitted design","Tiny Tapeout 9","Digital interface"],"discoverySources":["https://tinytapeout.github.io/tinytapeout-09/shuttle_index.json","https://tinytapeout.github.io/tinytapeout-ihp-25a/shuttle_index.json"],"evidence":{"readmeUrl":"https://github.com/MichaelMcCulloch1/tt09-verilog-Michael-ALU/blob/0648e618dedc0d3d33b031926681e6615c1c4658/info.yaml","licenseUrl":"https://raw.githubusercontent.com/MichaelMcCulloch1/tt09-verilog-Michael-ALU/0648e618dedc0d3d33b031926681e6615c1c4658/LICENSE","licenseSha256":"c71d239df91726fc519c6eb72d318ec65820627232b2f796219e87dcf35d0ab4","checkedAt":"2026-09-26T19:36:32.522581+00:00","notes":"Registry metadata import. License text matched a recognized root grant at the submitted revision; third-party files may have separate terms. Source metadata is author supplied. No build, fabrication, or measurement claim is made by Hub."},"sourceRevision":"0648e618dedc0d3d33b031926681e6615c1c4658","registry":"Tiny Tapeout","reviewMethod":"registry_metadata","metadataSha256":"5e1e8e6f286ae3c162e026ca346efb844bd3d8f374c82efe2ebc32bc5b1fcab1","aliases":["tt_um_michaelmcculloch_alu","tt09-verilog-Michael-ALU"],"type":"Submitted Design","stage":"RTL","sourceLabel":"github.com/MichaelMcCulloch1/tt09-verilog-Michael-ALU","status":"External index","activitySource":"https://github.com/MichaelMcCulloch1/tt09-verilog-Michael-ALU/blob/0648e618dedc0d3d33b031926681e6615c1c4658/info.yaml","activity":"See upstream documentation for releases and maintenance status.","cataloged":"Registry indexed 2026-09-26","licenseScope":"Registry metadata import. License text matched a recognized root grant at the submitted revision; third-party files may have separate terms. Source metadata is author supplied. No build, fabrication, or measurement claim is made by Hub.","accent":"blue","glyph":"MI","passport":null,"links":{"self":"/api/v1/resources/tt-77a25fab3b05","html":"/repo/tt-77a25fab3b05","evidence":"/api/v1/resources/tt-77a25fab3b05/evidence","runs":"/api/v1/resources/tt-77a25fab3b05/runs"}},"attribution":{"catalog":"https://hub.vlsi.kr","methodology":"https://hub.vlsi.kr/methodology","note":"Source documentation, license evidence, Hub reproduction and silicon reports are separate claims."}}