{"apiVersion":"1.0","data":{"id":"sv2v","name":"sv2v","owner":"Zachary Snow","source":"https://github.com/zachjs/sv2v","licenseSource":"https://github.com/zachjs/sv2v/blob/master/LICENSE","license":"BSD-3-Clause","description":"A converter from SystemVerilog to Verilog focused on synthesizable language constructs.","domains":["Digital"],"kind":"Tool","tasks":["Synthesis"],"language":"Haskell","target":"Synthesizable SystemVerilog-to-Verilog conversion","toolchain":"Yosys","tags":["SystemVerilog","Verilog","Conversion","Synthesis"],"discoverySources":["https://github.com/YosysHQ/oss-cad-suite-build"],"evidence":{"readmeUrl":"https://raw.githubusercontent.com/zachjs/sv2v/master/README.md","licenseUrl":"https://raw.githubusercontent.com/zachjs/sv2v/master/LICENSE","licenseSha256":"510af6b57a8830831a4b97eb41ddd02d6f05c9727b8083b6522d2c1706fc64c5","checkedAt":"2026-09-26T00:00:00Z","notes":"Fetched upstream README and license body; not run."},"type":"Open EDA","stage":"SYNTH","sourceLabel":"github.com/zachjs/sv2v","status":"External index","activitySource":"https://raw.githubusercontent.com/zachjs/sv2v/master/README.md","activity":"See upstream documentation for releases and maintenance status.","cataloged":"Metadata checked 2026-09-26","licenseScope":"Fetched upstream README and license body; not run.","accent":"blue","glyph":"SV","passport":null,"links":{"self":"/api/v1/resources/sv2v","html":"/repo/sv2v","evidence":"/api/v1/resources/sv2v/evidence","runs":"/api/v1/resources/sv2v/runs"}},"attribution":{"catalog":"https://hub.vlsi.kr","methodology":"https://hub.vlsi.kr/methodology","note":"Source documentation, license evidence, Hub reproduction and silicon reports are separate claims."}}