{"apiVersion":"1.0","data":{"id":"project-uray","name":"Project U-Ray","owner":"F4PGA","source":"https://github.com/f4pga/prjuray","licenseSource":"https://github.com/f4pga/prjuray/blob/master/LICENSE","license":"Apache-2.0","description":"An effort to document Xilinx UltraScale and UltraScale+ FPGA bitstream formats.","domains":["FPGA"],"kind":"Dataset/Benchmark","tasks":["Routing","Fabrication/Test"],"language":"Python · C++","target":"Xilinx UltraScale and UltraScale+ device databases","toolchain":"See upstream documentation","tags":["Xilinx","UltraScale","Bitstream","FPGA"],"discoverySources":["https://github.com/f4pga"],"evidence":{"readmeUrl":"https://raw.githubusercontent.com/f4pga/prjuray/master/README.md","licenseUrl":"https://raw.githubusercontent.com/f4pga/prjuray/master/LICENSE","licenseSha256":"cfc7749b96f63bd31c3c42b5c471bf756814053e847c10f3eb003417bc523d30","checkedAt":"2026-09-26T00:00:00Z","notes":"Fetched upstream README and license body; not run."},"type":"Benchmark","stage":"REPRO","sourceLabel":"github.com/f4pga/prjuray","status":"External index","activitySource":"https://raw.githubusercontent.com/f4pga/prjuray/master/README.md","activity":"See upstream documentation for releases and maintenance status.","cataloged":"Metadata checked 2026-09-26","licenseScope":"Fetched upstream README and license body; not run.","accent":"blue","glyph":"PR","passport":null,"links":{"self":"/api/v1/resources/project-uray","html":"/repo/project-uray","evidence":"/api/v1/resources/project-uray/evidence","runs":"/api/v1/resources/project-uray/runs"}},"attribution":{"catalog":"https://hub.vlsi.kr","methodology":"https://hub.vlsi.kr/methodology","note":"Source documentation, license evidence, Hub reproduction and silicon reports are separate claims."}}