{"apiVersion":"1.0","data":{"id":"picorv32","name":"PicoRV32","owner":"YosysHQ","source":"https://github.com/YosysHQ/picorv32","licenseSource":"https://github.com/YosysHQ/picorv32/blob/main/COPYING","license":"ISC","description":"A size-optimized configurable RISC-V CPU core implementing RV32IMC and RV32E options.","domains":["Digital","FPGA"],"kind":"IP/Design","tasks":["Architecture","Verification","Synthesis"],"language":"Verilog","target":"Small RISC-V CPU implementations","toolchain":"See upstream documentation","tags":["RISC-V","RV32","CPU","Verilog"],"discoverySources":["https://github.com/YosysHQ","https://github.com/YosysHQ/oss-cad-suite-build"],"evidence":{"readmeUrl":"https://raw.githubusercontent.com/YosysHQ/picorv32/main/README.md","licenseUrl":"https://raw.githubusercontent.com/YosysHQ/picorv32/main/COPYING","licenseSha256":"041ebc727233e5bf096dd41260cbb81014d3d29ca007a15f3b1807d4e9ff288e","checkedAt":"2026-09-26T00:00:00Z","notes":"Fetched upstream README and license body; not run."},"type":"Open Chip Design","stage":"RTL","sourceLabel":"github.com/YosysHQ/picorv32","status":"External index","activitySource":"https://raw.githubusercontent.com/YosysHQ/picorv32/main/README.md","activity":"See upstream documentation for releases and maintenance status.","cataloged":"Metadata checked 2026-09-26","licenseScope":"Fetched upstream README and license body; not run.","accent":"blue","glyph":"PI","passport":null,"links":{"self":"/api/v1/resources/picorv32","html":"/repo/picorv32","evidence":"/api/v1/resources/picorv32/evidence","runs":"/api/v1/resources/picorv32/runs"}},"attribution":{"catalog":"https://hub.vlsi.kr","methodology":"https://hub.vlsi.kr/methodology","note":"Source documentation, license evidence, Hub reproduction and silicon reports are separate claims."}}