{"apiVersion":"1.0","data":{"id":"chisel","name":"Chisel","owner":"CHIPS Alliance","source":"https://github.com/chipsalliance/chisel","licenseSource":"https://github.com/chipsalliance/chisel/blob/main/LICENSE","license":"Apache-2.0","description":"A Scala embedded HDL for parameterized RTL circuit generators that produce synthesizable Verilog for ASIC and FPGA logic.","domains":["Digital","FPGA"],"kind":"Tool","tasks":["Architecture","Synthesis"],"language":"Scala","target":"Parameterized digital hardware generation","toolchain":"Verilog","tags":["HDL","Scala","Generator","RTL"],"discoverySources":["https://github.com/chipsalliance","https://github.com/YosysHQ/oss-cad-suite-build"],"evidence":{"readmeUrl":"https://raw.githubusercontent.com/chipsalliance/chisel/main/README.md","licenseUrl":"https://raw.githubusercontent.com/chipsalliance/chisel/main/LICENSE","licenseSha256":"a750f7f60edf8ed0479e399ae319301131bf926875c794a517f3a83306b071ea","checkedAt":"2026-09-26T00:00:00Z","notes":"Fetched upstream README and license body; not run."},"type":"Open EDA","stage":"SYNTH","sourceLabel":"github.com/chipsalliance/chisel","status":"External index","activitySource":"https://raw.githubusercontent.com/chipsalliance/chisel/main/README.md","activity":"See upstream documentation for releases and maintenance status.","cataloged":"Metadata checked 2026-09-26","licenseScope":"Fetched upstream README and license body; not run.","accent":"blue","glyph":"CH","passport":null,"links":{"self":"/api/v1/resources/chisel","html":"/repo/chisel","evidence":"/api/v1/resources/chisel/evidence","runs":"/api/v1/resources/chisel/runs"}},"attribution":{"catalog":"https://hub.vlsi.kr","methodology":"https://hub.vlsi.kr/methodology","note":"Source documentation, license evidence, Hub reproduction and silicon reports are separate claims."}}