{"apiVersion":"1.0","data":[{"id":"Open Chip Design","label":"Open Chip Design","count":16},{"id":"RISC-V Core","label":"RISC-V Core","count":6},{"id":"Verification","label":"Verification","count":3},{"id":"Open EDA","label":"Open EDA","count":79},{"id":"Open PDK","label":"Open PDK","count":5},{"id":"FPGA Project","label":"FPGA Project","count":3},{"id":"Benchmark","label":"Benchmark","count":5},{"id":"Model & Library","label":"Model & Library","count":12},{"id":"Design Flow","label":"Design Flow","count":9},{"id":"Tutorial & Template","label":"Tutorial & Template","count":2},{"id":"Tool Distribution","label":"Tool Distribution","count":3},{"id":"Submitted Design","label":"Submitted Design","count":2105}],"attribution":{"catalog":"https://hub.vlsi.kr","methodology":"https://hub.vlsi.kr/methodology","note":"Source documentation, license evidence, Hub reproduction and silicon reports are separate claims."}}